An Efficient Hardware Accelerator to Handle Compressed Filters and Avoid Useless Operations in CNNs
DOI:
https://doi.org/10.26754/jji-i3a.201802800Resumen
Due to sparsity, a significant percentage of the operations carried out in Convolutional Neural Networks (CNNs) contains a zero in at least one of their operands. Different approaches try to take advantage of sparsity in two different ways. On the one hand, sparse matrices can be easily compressed, saving space and memory bandwidth. On the other hand, multiplications with zero in their operands can be avoided.
We propose the implementation in an FPGA of an architecture for CNNs capable of taking advantage of both, sparsity and filter compression.
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Publicado
2018-05-25
Cómo citar
Alcolea Moreno, A., Olivito, J., & Resano, J. (2018). An Efficient Hardware Accelerator to Handle Compressed Filters and Avoid Useless Operations in CNNs. Jornada De Jóvenes Investigadores Del I3A, 6. https://doi.org/10.26754/jji-i3a.201802800
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Artículos (Tecnologías de la Información y las Comunicaciones)