Advances in FPGA hardware generation with High Level Synthesis: models and programmability

Abstract

The inclusion of FPGAs for improving hardware generations has highlighted FPGAs as accelerators. This work shows two proposals focus on programmability and performance using High Level Synthesis (HLS) : 1) Based on the analysis and modeling of the functional units generated by compilers, with emphasis on memory and 2) Implementing frameworks that allow the efficient use of FPGA resources in domains such as computer vision.